As the demand for integrated circuits continues to rise, manufacturers labor to incorporate increasingly greater numbers of transistors onto each die. Integrated circuit memories often times have higher transistor densities than other types of circuits, and as a result, tend to push the leading edge of the technology envelope. The memories are typically organized into two dimensional arrays wherein each memory cell in the array is intersected by a row conductor and a column conductor. The two dimensional memory arrays are often times limited in memory cell density by the minimum line widths of the technology used to fabricate the array. As a result, improvements in the memory densities are achieved when the minimum feature sizes of the integrated circuit process used to fabricate the memories are decreased.
One popular type of memory is a read-only memory (ROM). The two most common types of ROMs are mask ROMs and field programmable ROMs. With mask ROMs, the information stored in each memory cell is permanently programmed during the fabrication process and cannot be subsequently changed. Field programmable ROMs are not programmed during the fabrication process and are more desirable because they enable end users to store a single part type which can be used in many applications.
One type of field programmable ROM includes memory cells which have a storage element and a control component. The storage elements typically have a high resistance to current flow and can be programmed to have a low resistance by application of a suitable voltage across the storage element. The programmed configuration can be sensed by application of a read voltage across the storage element and by comparing the current passed through the programmed storage element to the current passed through a non-programmed storage element.
One disadvantage of the two dimensional ROM arrays are leakage currents which tend to make accurate memory reads more difficult as the number of memory cells in the arrays are increased. For example, the row and column lines which intersect memory cells in the array travel the entire length of the array. If a particular row and column line are selected and the read voltage is applied, other storage elements positioned along the row line or along the column line can provide leakage currents which make it more difficult to detect the difference between the non-programmed and programmed configurations. One approach to limit the leakage currents is to separate the column lines into portions which are each separately addressable. To accomplish this, additional peripheral circuitry must be added to read and write the individual column line portions. While this approach can reduce leakage currents by reducing the number of unselected storage elements connected to each column line portion, the number of memory cells in the array must be decreased to make room for the additional read and write circuits.
In view of the above, there is a need for an improved memory which has greater memory cell densities and reduced leakage currents.